Company Name:



San Jose, CA

Approximate Salary:

Not Specified

Date Posted:

April 7, 2019

Senior Design Engineer

Job Description

This position will be responsible for micro-architecting and designing various subsystems that control multiple peripherals and perform critical functions in the chip. This role requires in depth knowledge of DFT, Debug, Boundary Scan and High Speed Interconnect Bus Architectures. Knowledge of NIOS CPU based Ecosystems is highly desirable. The main goal is to define a high performance subsystem which is able to efficiently communicate with other macros in the chip. The candidate needs to analyze performance in all the corner cases, design dedicated blocks to improve it, and work closely with the Verification and Firmware Development Teams to create the Test Plan.


Essential Functions
Write RTL code that can efficiently interface the device peripherals
Design for reusability; the RTL should be easily customizable through parameters, pass all the front-end design quality metrics and have supporting documentation
Develop a set of metrics to assess the performance (power, throughput, latency) of the subsystems in different use cases
Work with Firmware Developers to create testcases targeting the critical functions of each subsystem
Document the complete functionality and work with the Chip Architecture Team to cover all the uses cases
Develop the timing constraints and work with the Implementation Team to identify the bottlenecks in the flow
Work closely with the DFT Team for efficient test insertion with minimum performance degradation
Make sure all the security features are met and drive the required security compliance
Develop reference designs to validate all the use cases of the Subsystem

Required Education and Experience
BSEE required; MSEE preferred
Minimum 8 years of experience in Design, Verification, Synthesis, Static Timing Analysis of CPU-based Subsystems
Knowledge of chip design and implementation flow

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